In this thesis, a transceiver based on the C-PHY protocol is proposed to effectively increase the bandwidth with low power dissipation. The proposed transceiver includes an impedance calibrated transmitter with tri-level signaling, a crosstalk- cancelled receiver with an AC termination circuit, and a self-designed 3-wire transmission line with a characteristic impedance of 50 Ω. The active inductor is also introduced in the transceiver to improve the signal integrity. The prototype is fabricated in a 28-nm CMOS process with 3 pins, which achieves a high pin efficiency of 76%. The proposed transceiver operates at the encoded PRBS7 input of 8 Gsymbol/s, achieving a full data rate of 18.24 Gb/s considering the symbol efficiency, while consuming just 7.01 mW from a supply voltage of 1 V, and an excellent FOM (=Power/data rate) of 0.4 pJ/b is achieved.