In the first part, this thesis presents an overview of the CMOS on-chip rectifiers for RF energy harvesting. The pros and cons of different RF to DC rectifier topologies are investigated, compared, and summarized. All the topologies are simulated and optimized in a 65 nm CMOS process, with an input power range from –10 dBm to 4 dBm and a load resistor range from 10 kΩ to 1 MΩ. The simulated results show that the cross-connected (CC) topology exhibits the highest achievable power conversion efficiency (PCE) up to 65% (for rectifier only), while the CC topology with the threshold voltage cancellation technique and the MOS diode topology achieve 46.7% and 51%, respectively. Then, a dual-path CMOS rectifier with adaptive control for ultra-high frequency (UHF) RF energy harvesters is presented. The input power range with high power convention efficiency (high-PCE) of the rectifier is extended by the proposed architecture which includes a low-power path and a high-power path. The dual-path rectifier with an adaptive control circuit is fabricated in a 65 nm CMOS process. Operating at 900 MHz and driving a 147 kΩ load resistor, the measured PCE of this work can be maintained above 20% with an 11 dB input range from −16 dBm to −5 dBm, while only an 8 dB input range can be achieved with traditional single-path rectifiers. A sensitivity of −17.7 dBm is measured with 1 V output voltage across a capacitive load.