In the recent years, wireless communications technology is developed rapidly, wide bandwidth, low power dissipations and small chip size become the main requirements to the design for the ΣΔ ADCs applied in this field. Continuous-Time (CT) ΣΔ modulators turn to a preferred candidate and are extensively utilized in wireless communication systems due to the advantages wider bandwidth, lower power, smaller silicon area, lower switching noise and implicit anti-alias filtering over the Discrete-Time (DT) counterpart. In practical implementations, some non-idealities limit the performance of CT ΣΔ modulators which lead it to be difficult to achieve higher speed and resolution. Clock-jitter induced feedback pulse-width variation is one of the most serious problems, it can introduce feedback noise which increases In-Band-Noise (IBN) power and restricts ADC’s resolution. This thesis proposes two types of circuit techniques to achieve the clock-jitter insensitivity in the feedback of CT ΣΔ modulators. The common working mechanism is generating a jitter insensitive clock signal to control the feedback current. The difference is that one technique has the advantage of low power and easy implementation; the other technique has the insensitivity to the process variation. A design example for a 2nd order 1-bit CT ΣΔ modulator used in 3G WCDMA receivers is presented. The modulator is implemented in 65nm CMOS with 1V supply. The effectiveness of the proposed jitter insensitive feedback control techniques are adopted in the designed modulator and verified by the transistor-level simulation. The designed modulator achieves 68dB SNDR with the power consumption less than 5mW. With the proposed techniques, the clock-jitter tolerance can be up to 5%Ts for 10-bit ADC resolution requirement.