Power management integrated circuits (PMICs) are crucial components in electronic devices. Among which, DC-DC converters and low-dropout regulators (LDOs) are widely used in battery-powered applications. DC-DC converters feature high efficiency and large load current capability; however, they suffer from large voltage ripple and slow transient response. Therefore, LDOs, including digital LDO (DLDO) and analog LDO (ALDO), are widely used for point-of-load applications. Therefore, DC-DC and LDO cascade structure is a common solution for the power delivery network on board or on chip. This thesis can be divided into two parts, covering both the DC-DC and LDO designs. DC-DC converters can be categorized into two types: inductive DC-DC converter, e.g., buck converter, boost converter and buck-boost converter; or capacitive DC-DC converter e.g., switched-capacitor (SC). In recent years, hybrid DC-DC converters that consist of both inductor and capacitor have attracted much attention for their superior over traditional inductive and capacitive DC-DC converters. In this thesis, we proposed a hybrid switched-capacitor (SC)-parallel-inductor buck (CPL-Buck) converter with reduced inductor current IL. The proposed CPL-Buck converter reduces the voltage stress on the inductor by a series-connected flying capacitors C(F1) in phase 1 and reduces the current stress by a parallel-connected SC in both phase 1 and phase 2. Therefore, it effectively reduces the current ripple as well as the average current of IL, making it possible to use a small volume inductor to deliver large output current IOUT. Measurement results show that, for 1.2A maximum I(OUT), 3-4.2V input to 0.6-1V output, the proposed CPL-Buck obtains a peak efficiency of 92.9% and a peak current density of 0.3A/mm^2 with a power inductor as small as 1.6×0.8×0.8mm^3. Then, a fully integrated DLDO with adaptive current step size control is proposed for near/subthreshold voltage digital circuits. By dividing the main power PMOSs into ten blocks with different unit-cell sizes, the proposed DLDO can turn-on/-off small power PMOSs in light load and large ones in heavy load conditions. High regulation accuracy in a wide load range and fast transient response are hence achieved. The measured undershoot and overshoot voltages are only 53 and 37 mV, respectively, when the load current changes between 0 and 100 mA. To supply the noise-sensitive circuits, we presents a fully integrated flipped voltage follower (FVF) based LDO regulator with enhanced full-spectrum power supply rejection (PSR). We firstly studied three types of FVF LDO’s PSR performances, then we proposed a novel FVF LDO with a low-gain fast loop-1 for full spectrum PSR and a high-gain slow loop-2 to enhance the low frequency PSR. What’s more, we used dynamic compensation to push loop-2’s unit gain bandwidth (UGB) to higher frequency, thus further improved the PSR in ten of kHz to tens of MHz range. Measurement results show that the circuit achieves a low frequency PSR of –58 dB with the worst full-spectrum PSR of –9 dB in 20mA ILOAD with a 300 pF on-chip output capacitor. Further, with an UGB over 400 MHz, the proposed FVF LDO reaches 0.9 ns response time.